Yunhao Zhou's CV

Click to get PDF

Education

• M.S. in SJTU, 2022-2025
• B.S. in HUST, 2022

Research & Work experience

• 2024: Research Intern
  • Institution: National Center of Technology Innovation for EDA
  • Duties: Verilog representation learning in CDFG domain based on GNN, LLM based Verilog generation
• 2023-2024: Research Assistant
  • Institution: Institute of Computing Technology, Chinese Academy of Sciences
  • Duties: LLM-based verilog generation, LLM for Electronic System Design Automation, ML-based logic synthesis
• 2024: Software Intern
  • Institution: Nvidia Corporation
  • Duties: Internal software development for VLSI physical design
• 2023: Software Intern
  • Institution: X-EPIC Corporation
  • Duties: Software development for formal verification

Skills

• Programing Language: C/C++, Python, TCL
• Opensource system: ABC, Gem5
• IC design: Verilog, Cadence virtuoso, Quartus
• Development platform: linux

Publications

Speculative Decoding for Verilog: Speed and Quality, All in One

Liu Y, Xu C, Zhou Y, et al. Speculative Decoding for Verilog: Speed and Quality, All in One

Deeprtl: Bridging verilog understanding and generation with a unified representation model

Liu Y, Xu C, Zhou Y, et al. Natural language is not enough: DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation

Chang K, Chen Z, Zhou Y, et al. Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation.

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework

Chang K, Wang K, Yang N, et al. Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework[J]. arXiv preprint arXiv:2403.11202, 2024.